Integrated circuit (IC) chips include a stack of several levels or sequentially formed layers of material to define active devices (e.g., FETs) and passive devices (wirings, etc.). For example, a FinFET would include a gate dielectric material and metal gate materials formed on a semiconductor material. The metal gate materials would be protected by a capping material, with sidewall spacers provided on the sides of the gate dielectric material and metal gate materials. Source and drain regions are formed in or on the semiconductor material on sides of the gate material.
As FinFETs continue to shrink in size (e.g., 22 nm and beyond), a work-function metal chamfering process is necessary to achieve a desired threshold voltage (Vth). However, the nominal gate conductor (PC) critical dimension (CD) is challenging for the chamfering process and subsequent metal fill process at these smaller technology nodes. And, as gate dimensions shrink, gate resistance increases and more low-resistance metal such as tungsten (W) is needed relative to higher resistance work-function metal (WFM) such as TiN. Moreover, at such technology nodes, the source and gate contact formation process may result in shorting to the gate material and/or to the gate dielectric material.